This invention relates to a linear resistance element suitable for use in integrated circuits, particularly integrated 10 circuits that require a large linear resistance independent of voltage potential applied across the resistive element.
Long lines of heavily-doped polysilicon have been used to form resistors in integrated circuits. However, the relatively low resistivity of this material limits the values of resistance which can be obtained. Lightly-doped regions of silicon, such as p-well diffusions or implants, have been used to form resistors with higher values. However, these resistances are not particularly accurate or reproducible and are susceptible to fixed charge or states, as for example at interfaces, which can affect their linearity and resistance values. Depletion-mode transistors have been used as resistive loads but their current-voltage relationships are significantly nonlinear. Large, linear resistances are usually regarded as impractical in IC technology.
U.S. Pat. No. 4,001,612 discloses a linear resistance element for LSI circuitry. The circuit of this invention is composed of two similar depletion type, field effect transistors having their source electrodes connected together and to a voltage source. Their drain electrodes are similarly connected together and to the other side of the voltage source. The gates of the two FET's are connected one to the common drain electrode and the other to the common source electrode. The resistance of this FET pair is substantially independent of the circuit current or voltage. A limitation of this linear resistance element is that the channels of the two FET's are connected in parallel 11 which results in a linear resistance element having less resistance than would otherwise be provided by resistive elements connected in series within the same area.
U.S. Pat. No. 4,667,216 discloses an electric resistor consisting of at least two simultaneously produced monolithically combined MIS field-effect transistors for integrated circuits. Each transistor has a source electrode and a drain electrode that define a source-drain path, a gate terminal, and a channel width to channel length ratio. The transistors are connected in series with each other through the source-drain paths. The gate terminals of each transistor are connected to one of the source and drain electrodes. The gates of each transistor forming a pair are connected together and to the source and drain electrodes that connect each transistor. The channel width to channel length ratios of each transistor comprising a transistor pair are different. This configuration provides a two terminal resistor such that the transistors are graded and balanced against each other with respect to the channel width to channel length ratios. In the operation of this resistor, a given fixed potential V.sub.M is applied to one of the resistor terminals. A first voltage (V.sub.1 -V.sub.M) and a second voltage (V.sub.m -V.sub.2) are alternately applicable to the other terminal wherein (V.sub.1 -V.sub.M)=-(V.sub.M -V.sub.2). Equal and oppositely directed current flows through the resistor when the first voltage is applied as compared to when the second voltage is applied. However, because one of the 11 terminals must be at a fixed potential, this device is unsuitable for applications requiring linearity independent of potential.
Thus, there is a need for a linear resistor suitable for application in integrated circuits which functions independently of potential and which provides greater resistance for a given number of transistors having a particular geometry than is available using present linear resistance elements.